Duolog Technologies Pioneers I/O Fabric Generator for Complex SoC Designs

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Fri Jun 6, 2008 2:52pm EDT

  DUBLIN, IRELAND, Jun 06 (MARKET WIRE) -- 
 Duolog Technologies, the Collaborative Design Automation(TM) company, announced
its new
Spinner(TM) I/O fabric generation tool for automated, bug-free I/O fabric
synthesis of complex SoCs. Duolog will introduce and demonstrate Spinner at
the 45th annual DAC Design Automation Conference in Booth #241.

    Duolog's Spinner auto-generates and validates the RTL for the complete I/O
layer
of an IC from a single-source specification. Using Spinner's Perfect By
Construction(TM) methodology, SoC designers can eliminate I/O bugs and
greatly simplify the integration effort -- with up to 3x fewer resources, 5x
schedule reductions and radically improved quality through sign-off level
collaboration on incremental changes.

    "Every aspect of I/O integration is growing in complexity," said Ray Bulger,
co-founder and CEO of Duolog Technologies. "The number of pins is growing,
the number of functions per pin is growing, DFT is far more complex, I/O cells
require much more granular control, and power logic and control needs to be
embedded. In the midst of this spiraling complexity, SoC design teams are coming
under enormous pressure to deliver and maintain a bug-free design right from the
start. Quite simply, I/O design bugs can delay system validation, and silicon
bugs can kill the chip. At 45nm, one re-spin typically costs more than $4
million, and a three-month re-spin delay can result in a 25 percent loss in
revenue. That's why we've built Spinner for fully automated, 1-Click Release of
complex I/O fabrics that are Perfect By Construction."

    Duolog's Spinner enables a fully automated, bug-free 1-Click Release(TM)
with
standardized tool interfaces, extensive coherency checking and a powerful
generator framework that delivers bug-free code and specifications.

    "The complexity of SoC platform designs is dwarfing the capabilities of
semiconductor companies' in-house tools, semi-automated EDA tools
primarilydeveloped during the 1990s and even more recent rules-based integration
tools," said
Mary A. Olsson, Chief Analyst for Gary Smith EDA. "Duolog's approach to
automating
I/O fabric generation offers a refreshing alternative that can eliminate the I/O
bugs that plague today's SoC designs."

    Spinner's advanced I/O fabric generation features include:


--  IP-XACT compliant interfaces for Core, Chip, Die and Package as well
    as I/O layer primitives, such as I/O, DFT and BSR cells

--  Complete SoC I/O Layer specification IDE for pin muxing, I/O Cell
    control, BSR and package definition

--  Coherency checking to perform an exhaustive range of checks on the I/O
    specification

--  Auto-Generation of I/O fabric RTL, documentation, validation and
    software views and IP-XACT interfaces.
    

    
"TI has been using Duolog's integration tools since 2002 on our OMAP
SoCdevelopments," said Ziad Mansour, wireless SoC Development manager for Texas
Instruments. "Spinner fully automates the creation and management of the I/O
layers and greatly enhances the quality and timeliness of our deliverables."

    Eclipse-based Spinner runs on Windows, Linux or Solaris and is highly
interoperable with existing design flows through standards-based interfaces.

    At DAC, Duolog's CTO, Dave Murray, will explore Spinner's capabilities in an
User Group presentation led by Texas Instruments -- "Using IP-XACT in complex
SoC
I/O Integration" -- on Tuesday, June 10 from 2 to 4 pm. For more information,
visit: http://www.ipxact-ug.org/meetings.htm.

    Pricing and Availability

    Duolog's Spinner is available immediately with multiple licensing options.

    About Duolog Technologies

    Duolog, The Collaborative Design Automation(TM) Company, is a pioneering
developer
of groundbreaking EDA tools that enable the flawless and rapid integration of
today's increasingly complex SoC, ASIC and FPGA designs. Duolog's Socrates Chip
Integration Platform enables IC designs that are Perfect By Construction(TM).
The world's leading IP and IC/SoC development companies rely on Duolog tools to
automate their chip integration processes -- eliminating bugs, shrinking design
cycles and drastically reducing the risk of costly delays and respins. For
more information, visit http://www.duolog.com.

    Spinner, Collaborative Design Automation, Perfect by Construction and
1-Click
Release are trademarks of Duolog Technologies Ltd.

    

Contact:
Zee Zaballos
ZNA Communications
+1.831.425.1581, ext. 201
Email Contact
http://www.zna.com

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