Virage Logic Sees Strong Adoption of Company`s Broad 40nm IP Product Portfolio

More Than 10 Customers Rely on Virage Logic`s 40nm G and LP Products to Reduce
Design Risk and Speed Time-to-Market
FREMONT, Calif.--(Business Wire)--
Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted IP
partner, today announced that since being named TSMC`s 40-namomenter (nm) early
development partner in 2007, the company has seen strong adoption of its
extensive 40nm product portfolio. Comprising embedded SRAMS, embedded memory
test and repair, logic libraries, and memory development software, the Company`s
silicon-proven 40nm product offering has been designed to optimize area,
performance, power and yield. Today, more than ten customers rely on Virage
Logic`s 40nm product portfolio to design more efficient chips more quickly and
with less risk as they develop products for such end markets as graphics,
consumer, enterprise, networking, wireless, and handheld.

"Virage Logic has a long, proven track record of being first-to-market at the
advanced process technologies and with our extensive 40nm product portfolio, we
are proud to offer our customers a competitive advantage at this advanced
process node," said Brani Buric, Virage Logic`s executive vice president,
marketing and sales. "Our SiWare Memory and SiWare Logic products provide
designers with a comprehensive dashboard of options for the flexibility needed
to efficiently manage design tradeoffs and meet customers` specific
requirements. For example, this dashboard enables our customers to achieve up to
a 90% power savings in 40nm G and LP process nodes. Our STAR Memory System
embedded test and repair offering extends the value we can deliver by enabling
customers to dramatically ramp to volume at advanced nodes such as 40nm," he
said. "Finally, our product portfolio is supported by a range of engagement
models to best meet the requirements of our fabless, integrated device
manufacturer (IDM) and foundry customers."

"TSMC selected Virage Logic as an early development partner at 40nm as a
continuation of our collaboration in technologies ranging from 250nm to 40nm.
Virage Logic and TSMC work closely to qualify IP through both Virage Logic`s
procedures and TSMC`s procedures including silicon validation of these advanced
technology IP solutions," said Dan Kochpatcharin, deputy director, IP Portfolio
Marketing at TSMC. "These extensive silicon quality report results are available
to designers of advanced SoCs for review when choosing Virage Logic`s broad IP
portfolio on TSMC`s 40nm process."

"We have been working with Virage Logic to meet our customer`s 40nm
ultra-low-power SoC requirements," said Prasad Subramaniam, vice president of
design technology at eSilicon Corporation. "By utilizing Virage Logic`s SiWare
Memory product line, we expect to be able to provide our customers with a
competitive advantage that includes first time silicon success and accelerated
time-to-volume production."

"With the inclusion of Virage Logic`s 40nm SiWare Memory compilers as part of
our overall LSI 40nm Memory capability, LSI has continued its partnership with
Virage Logic," said Don Friedberg, director of foundation IP at LSI. "We are
using Virage Logic`s feature-rich IP, including embedded memories for power
minimization and the STAR Memory System for embedded memory built-in test and
repair, to develop solutions that meet our customers` quality and performance
requirements."

"Virage Logic is an essential IP partner, spanning four process generations from
130nm to 40nm," said Shai Cohen, co-founder, vice president of operations and
engineering at Mellanox Technologies. "With their commitment to technology
leadership and quality, Virage Logic ensures we consistently achieve first time
silicon success, which is a tremendous competitive advantage for our
industry-leading, performance end-to-end connectivity solutions for the
high-performance computing and enterprise data center markets."

"We first selected Virage Logic`s 65nm SiWare Memory offering because it
provided the best power and density specs to meet our stringent design
requirements. We also took advantage of the compiler configurability for
performance optimization and the STAR Memory System for testability," said
Bradley Masters, vice president of engineering for Solarflare Communications.
"With the availability of even more power management capabilities in the 40nm
SiWare Memory products, the choice to move to 40nm with Virage Logic was easy.
We are confident that our forthcoming 40nm 10GBASE-T transceiver products will
be very robust with very compelling low levels of power consumption."

About Virage Logic`s Memory and Logic Products

The SiWare product line, first introduced in October 2007 for the 65nm process,
has been proven to address the increasingly complex design requirements that are
placed on physical IP at advanced processes. The power-optimized memories for
advanced processes minimize both static and dynamic power consumption and
provide optimal yields. SiWare High-Density memory compilers are optimized to
generate memories with the absolute minimum area. SiWare High-Speed memory
compilers are designed to help designers achieve the most aggressive critical
path requirements. Compile-time options for process threshold variants, power
saving modes, read and write margin extensions, ultra-low voltage operation, and
innovative design for at-speed test enable SoC designers to configure optimal
solutions for their specific design requirements.

All SiWare memories are fully supported by Virage Logic`s STAR Memory System,
the company`s flagship embedded memory test and repair system that may be used
with Virage Logic memories as well as with other commercially available or
internally developed memories. For repair purposes, the STAR Memory System
deploys foundry-developed eFuse for repair signature storage. The STAR Memory
System employs test algorithms tailored for advanced processes for higher
product reliability and accelerated time-to-yield.

The SiWare Logic product line includes yield-optimized standard cells for a wide
variety of design applications at 40nm with multiple threshold process variants.
SiWare Logic libraries offer three separate architectures to optimize circuits
for Ultra-High-Density, High-Speed, or general use. SiWare Logic Ultra-Low-Power
extension libraries also provide designers with the most advanced power
management capabilities.

For further information about Virage Logic`s silicon-proven 40nm product
portfolio, or to request silicon validation reports, please visit
www.viragelogic.com/SurePathTo40nmSuccess or email Virage Logic at
info@viragelogic.com.

About Virage Logic

Virage Logic is a leading provider of semiconductor intellectual property (IP)
for the design of complex integrated circuits. The company`s highly
differentiated product portfolio includes embedded SRAMs, embedded NVMs,
embedded memory test and repair, logic libraries, memory development software,
and interface IP solutions. As the industry`s trusted semiconductor IP partner,
foundries, IDMs and fabless customers rely on Virage Logic to achieve higher
performance, lower power, higher density and optimal yield, as well as shorten
time-to-market and time-to-volume. For further information, visit
http://www.viragelogic.com.

All trademarks are the property of their respective owners and are protected
herein.

Virage Logic Corporation
Sabina Burns, 510-743-8115
sabina.burns@viragelogic.com
or
McClenahan Bruer Communications
Tarah Hartzler, 503-546-1014
tarah@mcbru.com

Copyright Business Wire 2009