Lattice's New Mixed Signal Design Software Simplifies Platform Management Design

HILLSBORO, OR, Jul 18 (MARKET WIRE) --
Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced release
6.1 of its PAC-Designer(R) mixed signal design software, with updated
support for Lattice's Platform Manager(TM), Power Manager II and
ispClock(TM) devices. Users designing with Platform Manager devices will
now have access to the Lattice Diamond(R) 1.3 software design
environment, which was also announced today. This integration of the
PAC-Designer 6.1 and Diamond 1.3 design software tools will make more
advanced digital design options available with Platform Manager products.
An automated simulation environment, not previously available to Platform
Manager designers, is a primary benefit of the design software
integration.

"With the integration of PAC-Designer 6.1 and Lattice Diamond 1.3
software, our customers will be able to design and simulate Platform
Manager devices at an even higher level of productivity while maintaining
the ease of use for which PAC-Designer software is widely recognized,"
said Shakeel Peera, Lattice Director of Marketing for Silicon and
Solutions.

New Automated Simulation Capability
Whether testing the functionality of
critical analog I/O pin functions controlled by the Platform Manager's
internal CPLD, or checking the integration of enhanced digital control
functions coded in Verilog or VHDL within the Platform Manager's FPGA
control section, PAC-Designer 6.1 software integrates seamlessly with
Diamond 1.3 design tools to compile the entire design, create the
necessary stimulus template file and then automatically generate initial
timing waveforms within the Aldec Active-HDL simulator. This previously
complex, manual design flow has been optimized and automated in
PAC-Designer 6.1 software to generate all the necessary design files and
deliver the initial timing flow diagram with just the click of a mouse.

Comprehensive Analog and Digital Design Support
PAC-Designer 6.1
software provides a GUI-based design methodology for analog engineers
that uses intuitive dialog boxes to configure the Platform Manager's
analog sections; LogiBuilder design methodology to integrate power
management functions into the on-chip CPLD; and LogiBuilder or Lattice
Diamond Verilog/VHDL design methodology to integrate digital board
management functions into the FPGA section of the Platform Manager
device.

PAC-Designer 6.1 software includes four reference designs specifically
targeted for the Platform Manager development kit, including Fault
Logging and Monitoring, Enhanced Closed-loop Trim, Long Delay Timers and
ADC Voltage Measurement. Eleven more reference designs compatible with
Platform Manager devices are available on the Lattice website at
http://www.latticesemi.com/products/powermanager/platformmanager/,
including, among others, PWM Fan Control, Connecting an I2C Slave to SPI
Master Bridge and a BSCAN1 Multiple Scan Port Addressable Buffer.
Thirty-one additional design examples are also available from directly
within PAC-Designer 6.1 software that provide instructions and solutions
for Power Manager II and ispClock devices.

Third Party Design Tool Support
The integrated PAC-Designer 6.1 and
Lattice Diamond 1.3 software includes the Synopsys Synplify Pro advanced
FPGA synthesis for Windows. Aldec's Active-HDL Lattice Edition II
simulator is also included for Windows.

In addition to the tool support provided by the OEM versions of Synplify
Pro and Active-HDL, Lattice devices are also supported by the full
versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics
ModelSim SE and Precision RTL synthesis also support Lattice devices.

About the Platform Manager Family
Named 2010 "Product of the Year" by
Electronic Products magazine, the Platform Manager product family
consists of two devices, the LPTM10-1247 and LPTM10-12107. The
LPTM10-1247 device can monitor 12 voltage rails and supports 47 combined
digital inputs and digital outputs, while the LPTM10-12107 monitors up to
12 voltage rails and supports 107 combined digital inputs and digital
outputs. Functionally, these devices include both a power management
section and a digital board management section. The power management
section consists of a programmable threshold, precision differential
input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD,
programmable hardware timers, a 10-bit analog to digital converter and a
trim block for the trimming and margining of supplies. The digital board
management section consists of a 640-LUT FPGA and programmable logic
interface I/O.

Pricing and Availability
PAC-Designer 6.1 and Lattice Diamond 1.3
software are available immediately for free download from the Lattice
website at
http://www.latticesemi.com/products/designsoftware/pacdesigner/index.cfm.
Once downloaded and installed, PAC-Designer 6.1 software requires no
license. Lattice Diamond 1.3 software can be used with either the Lattice
Diamond free license or the Lattice Diamond subscription license. The
Lattice Diamond free license can be immediately generated upon request
from the Lattice website and provides no cost access to the Platform
Manager product family as well as many other popular Lattice devices such
as the MachXO2(TM) and MachXO(TM) PLD families, the LatticeXP2(TM) FPGA
family and the LatticeECP2(TM) FPGA family. The Lattice Diamond free
license enables Synopsys Synplify Pro for Lattice synthesis as well as
the Aldec Lattice Edition II mixed language simulator.

About Lattice Semiconductor
Lattice is the source for innovative FPGA,
PLD, programmable Power Management and Clock Management solutions. For
more information, visit www.latticesemi.com.
Follow Lattice via
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Lattice Semiconductor Corporation, Lattice (& design), L (& design),
PAC-Designer, ispClock, LatticeXP2, Lattice Diamond, MachXO, MachXO2,
LatticeECP2, Platform Manager and specific product designations are
either registered trademarks or trademarks of Lattice Semiconductor
Corporation or its subsidiaries in the United States and/or other
countries.

GENERAL NOTICE: Other product names used in this publication are for
identification purposes only and may be trademarks of their respective
holders.

EDITORIAL/READER CONTACT:
Brian Kiernan
Corporate Communications Manager
Lattice Semiconductor Corporation
503-268-8739 voice
503-268-8688 fax
brian.kiernan@latticesemi.com

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