HENDERSON, Nev.--(Business Wire)--
Aldec Corporation, a leader in RTL Simulation and Electronic Design Automation
(EDA), announces a low-cost Linux RTL Simulator today. Aldec unveils a new
configuration that supports both Linux and Windows mixed-language VHDL/Verilog
simulation. Riviera-PRO LV is a multi-platform RTL and gate-level simulator that
supports IEEE VHDL, Verilog and SystemVerilog (Design) IEEE standard, Xilinx
SecureIP and VHDL/Verilog IP encryption. The new configuration has no
limitations on ASIC or FPGA device support and includes an advanced waveform
toolset and fast debugging.
Availability
Riviera-PRO LV is available today as a perpetual or time-based floating license;
time-based pricing starts under $5,000 (USD). To learn more about Riviera-PRO
LV, go to: http://www.aldec.com/products/rivierapro.
About Aldec
Aldec Corporation is an industry-leader in Electronic Design Verification and
offers a patented technology suite including: RTL Design, RTL Simulators,
Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254
Functional Verification and Military/Aerospace solutions. Aldec is a privately
held corporation and employs approximately 200 people worldwide.
Riviera-PRO and Aldec are trademarks of Aldec Corporation. All other trademarks
or registered trademarks are property of their respective owners.
Aldec Corporation, Henderson
Lori Nguyen, 702-990-4400, ext. 254
Director of Marketing
Lorin@aldec.com
Copyright Business Wire 2009
