Key Developments For Cadence Design Systems, Inc.
Cadence Design Systems, Inc. (CDNS.O) (Nasdaq)
Cadence Design Systems, Inc. Expand SoC Design Alliance With Toshiba Corporation
Cadence Design Systems, Inc. announced that it has expanded the scope of its recently announced relationship with Toshiba Corporation for COT (customer-owned tooling) and SoC design targeting the growing and increasingly complex mobile and consumer markets. This new broader relationship will include technologies such as chip planning of early-stage SoC designs utilizing Cadence Chip Planning system, DRC/LVS/ERC using the Cadence Physical Verification System, and acceleration of mixed signal design simulations with parallel processing utilizing Cadence Virtuoso Advanced Parallel Simulator.
Exar Selects Cadence Design Systems, Inc. As Mixed Signal EDA Provider
Cadence Design Systems, Inc. announced that Exar Corporation has signed an expanded business agreement to establish Cadence as its leading chip planning and mixed-signal design solutions provider. As a result of the new multi-year agreement, the Cadence Virtuoso and Encounter platforms, as well as the Cadence Chip Planning Solution, will make up Exar's key mixed-signal design environment for designs at 65 nanometers and below. With the new agreement, Exar has chosen the Cadence Virtuoso platform for its analog and custom design and implementation technology. Additionally, the company will use Cadence Multi-mode Simulation technology for RF, FastSpice, and mixed-signal simulations. Exar will use the Cadence Encounter Digital Implementation System for digital design prototyping and floorplanning. And lastly, Exar has adopted the Cadence Chip Planning Solution as the standard for its IC conceptualization, analysis, and planning activities across the organization.
Cadence Design Systems, Inc. Issues Q4, FY 2009 Guidance; EPS Guidance Above Analysts' Estimates
Cadence Design Systems, Inc. announced that for the fourth quarter of 2009, it expects total revenue in the range of $215 million to $225 million. Fourth quarter GAAP net loss per diluted share is expected to be in the range of $(0.08) to $(0.06). Net income per diluted share using the non-GAAP measure is expected to be in the range of $0.02 to $0.04. For fiscal 2009, the Company expects total revenue in the range of $845 million to $855 million, on a GAAP basis, net loss per diluted share for fiscal 2009 is expected to be in the range of $(0.66) to $(0.64) and the non-GAAP net loss per diluted share for fiscal 2009 is expected to be in the range of $(0.10) to $(0.08). According to Reuters Estimates, analysts are expecting the Company to report revenue of $221 million and EPS of $0.01 for fourth quarter 2009; revenue of $852 million and EPS of $(0.14) for fiscal 2009.
Cadence Design Systems, Inc. And ARM Holdings Plc Collaborate To Increase Engineer Productivity And Drive Down Time To Market For SoC Integration
Cadence Design Systems, Inc. and ARM Holdings Plc announced that the two companies have entered into a strategic collaboration to create SoC design flow that will accelerate time to market and lower the cost of SoC integration and verification. Under the terms of the agreement, the Cadence Chip Planning System and Cadence Incisivefunctional verification solutions will be combined with ARM AMBA Designer, Performance Exploration tools and Network Interconnect IP.
SMIC Adopts Cadence Design Systems, Inc.'s Cadence DFM Solutions For 65- And 45-Nanometer IP/Library Development And Full Chip Production
Cadence Design Systems, Inc. announced that Semiconductor Manufacturing International Corporation (SMIC) has adopted Cadence Litho Physical Analyzer and Cadence Litho Electrical Analyzer to more accurately predict the impact of stress and lithographic variability on the performance of 65- and 45-nanometer semiconductor designs.
